Design and Transient Analysis of a Low-Power High-Data-Activity Dual-Edge Triggered Flip-Flop Using GPDK 90 nm Technology

Author

B. S. Vindhyavali, B. Kavya

Abstract

 Flip-flops are essential sequential elements in digital integrated circuits, where their power consumption, speed, and operational reliability significantly influence overall system performance. Dual-edge triggered flip-flops provide an alternative to conventional single-edge triggered designs by capturing input data at both rising and falling edges of the clock signal. This work presents the transistor-level implementation and transient analysis of a Low-Power High-Data-Activity Dual-Edge Triggered Flip-Flop (LPHD-DET FF) using GPDK 90 nm technology. The design is implemented using Cadence Virtuoso, following the latch-multiplexer-based True Single-Phase Clocking (TSPC) architecture. The circuit is evaluated through transient simulation by applying clock and data input signals and observing the corresponding output response. The simulation waveforms are analyzed to examine the functional behaviour of the flip-flop under the applied input conditions. This implementation study provides a basis for further evaluation of its power consumption, propagation delay, and energy efficiency in CMOS-based digital applications.

Keywords

Dual-Edge Triggered Flip-Flop, LPHD-DET, TSPC, GPDK 90 nm, Cadence Virtuoso, CMOS, Transient Analysis.

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References

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