Secure and Energy-Efficient Hardware Design for Post-Quantum Cryptographic Algorithms in IoT Edge Devices

Author

Mr. Manish Jain

Abstract

  The impending advent of cryptographically relevant quantum computers (CRQCs) threatens the fundamental security posture of modern Internet of Things (IoT) ecosystems by invalidating public-key infrastructure (PKI) based on RSA and Elliptic Curve Cryptography (ECC). In response, the National Institute of Standards and Technology (NIST) has standardized Post-Quantum Cryptography (PQC) primary algorithms, including ML-KEM (CRYSTALS-Kyber) for key encapsulation and ML-DSA (CRYSTALS-Dilithium) for digital signatures. However, transitioning PQC algorithms to resource-constrained IoT edge devices introduces severe hardware overheads in energy consumption, memory footprint, operational latency, and vulnerability to Physical Side-Channel Attacks (SCA) and Fault Injection Attacks (FIA). This paper presents a holistic hardware design methodology for integrating PQC algorithms into ultra-low-power IoT edge processors. We investigate domain-specific vector coprocessors, domain-optimized Number Theoretic Transform (NTT) multipliers, hybrid SRAM-eMRAM memory architectures, and Dynamic Voltage and Frequency Scaling (DVFS) frameworks. Furthermore, we evaluate lightweight hardware countermeasures against power analysis (DPA/CPA) and electromagnetic leakage (EMA), demonstrating a zero-latency masking unit that preserves energy efficiency. Experimental evaluations on 22nm FD-SOI and 45nm CMOS technology nodes show a 7.8x speedup in NTT polynomial multiplication and a 64% reduction in overall energy per execution cycle, achieving robust quantum security under a 15 mW energy budget.

Keywords

Post-quantum cryptography, NIST PQC standardization, Lattice-based cryptography, Hardware design, Cryptographic accelerators

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References

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