A Self-Repairing Asynchronous Digital Architecture Using Dynamic Logic Reconfiguration

Author

Mr. Manish Jain

Abstract

 As integrated circuits scale into sub-10nm regimes, traditional synchronous digital architectures face severe challenges regarding localized thermal hot-spots, clock skew, process-voltage-temperature (PVT) variations, and high rates of transient and permanent hardware faults. This paper presents a novel self-repairing asynchronous digital architecture that combines delay-insensitive Quasi-Delay-Insensitive (QDI) asynchronous circuit design with real-time dynamic logic reconfiguration. By eliminating global clock networks, the proposed architecture inherently absorbs variable switching delays induced by structural damage and aging. A fine-grained built-in self-test (BIST) unit continuously monitors pipeline handshakes, isolating faulty functional blocks upon error detection and dynamically re-routing data streams through spare programmable logic clusters. Simulation results demonstrate a 99.4% fault recovery rate with less than 12% silicon area overhead and zero operational downtime, providing a robust model for ultra-reliable computing applications in harsh environments.

Keywords

Asynchronous digital architecture, Clockless circuits, Self-timed systems, Self-repairing hardware, Fault-tolerant architecture

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References

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