A Systematic Literature Review on Hardware Trojan Horse: Threat, Prevention, Detection Techniques, and Future Directions

Author

Abdulkabir Adamu, S. O. Subairu, M. D. Noel , Ahmad Sulieman, Ahmad Abubakr Yusuf

Abstract

 Hardware Trojan horses pose a serious threat to the security and reliability of modern integrated circuits (ICs), as they can be covertly inserted at various stages of the IC life cycle including specification, design, fabrication, testing, assembly, and deployment and remain dormant until triggered. The increasing use of third-party intellectual property cores, outsourced fabrication, and global supply chains has significantly expanded the hardware attack surface. This study presents a systematic literature review of hardware Trojan threats, prevention strategies, insertion points, trigger mechanisms, payload behaviors, detection techniques, and future research directions, guided by five objectives: (i) identifying the major threats posed by hardware Trojans in modern hardware systems; (ii) examining the prevention strategies proposed across the IC life cycle; (iii) analyzing common insertion points, trigger mechanisms, and payload behaviors; (iv) identifying the major challenges and research gaps in existing prevention and detection approaches; and (v) highlighting future research directions for improving hardware Trojan detection and prevention. Using the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) framework, peer-reviewed studies published between 2014 and 2026 were systematically identified and analyzed, resulting in 55 articles included in the final review. The literature is categorized by Trojan behavior and detection methodology, including logic testing, side-channel analysis, run-time monitoring, and machine learning-based approaches. The review reveals sustained research growth from 2018 onward, with a peak around 2020. The findings show that, despite considerable progress, no single detection technique is capable of identifying all categories of hardware Trojans, because each approach exhibits limitations in detection coverage, scalability, computational complexity, implementation overhead, or susceptibility to stealthy Trojan designs. Furthermore, machine learning-based detection methods remain constrained by the absence of standardized benchmark datasets, limited real-world validation, inconsistent evaluation metrics, and poor generalization across hardware platforms. Other persistent challenges include the heavy concentration of research on post-fabrication detection, high area and power overheads of prevention techniques, limited protection along the global semiconductor supply chain, and the lack of integrated end-to-end defense frameworks spanning the entire IC life cycle. Based on these findings, the review recommends future research on standardized benchmarking frameworks and publicly available datasets, hybrid detection models that integrate structural, functional, and side-channel information, explainable machine learning techniques, lightweight real-time detection for resource-constrained devices, and end-to-end security frameworks that protect ICs throughout specification, design, fabrication, testing, assembly, deployment, and operation.

Keywords

Hardware Trojans; Integrated Circuit Security; Trojan Detection Techniques; Side-Channel Analysis

Full Text:

Download Paper PDF

References

Share your valuable work from Social Media Buttons